The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal or by enlarging or constricting the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1A illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor.
The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1A.
A thin dielectric layer is disposed on the substrate above the channel, and a “gate” structure (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.)
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications.
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors are used, often paired with one another.
While particular n- and p-type dopants are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
U.S. Pat. No. 3,387,286 (IBM; 1968) discloses field effect transistor memory. The memory is formed of an array of memory cells controlled for reading and writing by word lines and bit lines which are connected to the cells. Each cell is formed using a single FET and a single capacitor. The gate electrode of the FET is connected to the word line, the source terminal is connected to the bitline, and the drain terminal is connected to one of the (two) electrodes of the capacitor. The other electrode of the capacitor is connected to a reference potential. Information is stored by charging the capacitor through the transistor, and information is read out by discharging the capacitor through the transistor. During a “write” operation, the wordline which is connected to the gate of the transistor is energized to render the transistor conductive between source and drain. If a “zero” is to be stored, the bitline is not energized and the capacitor is not charged. If a “one” is to be stored, the bitline is energized and the capacitor is charged to substantially the potential (voltage) of the bitline signal. During “read” operations, only the wordline is energized and a signal is transmitted to the bit lie if a “one” has been stored previously (the capacitor is charged). Since the charge on the capacitor leaks off, it is necessary to periodically regenerate the information stored in the memory.
This “regeneration” is generally done by reading a cell before sufficient time has elapsed for the charge to leak off to a point where it is unreadable and, if the read indicates that the capacitor was charged, it is recharged. This “refresh” of the cell's contents may have to be done several times per second, depending on the cell's “retention time”. The dynamic nature of maintaining data stored in the memory cells gives rise to the nomenclature “dynamic” random access memory, of DRAM.
Memory Array Architecture, Generally
Dynamic random access memory (DRAM) is a type of random access memory that usually stores data as electrical charges in a capacitor structure associated with a transistor. Since capacitors leak charge (generally, a capacitor is only useful for temporarily storing an electrical charge), the information (data) eventually fades unless the capacitor charge is refreshed (read, and re-written) periodically, such as every 64 ms (milliseconds). DRAM is usually arranged in an array of one capacitor and transistor per “cell”.
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
FIG. 1B illustrates an array of DRAM cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). (Each DRAM cell is shown as comprising a FET and a capacitor.) For example, in the memory cell “e”, the FET has its gate connected to WL(n), its source is connected to BL(n), and its drain connected to one terminal of a capacitor. The other terminal of the capacitor is connected to ground. The nine memory cells (“a” through “i”) illustrated in FIG. 1B are exemplary of many millions of memory cells that may be resident on a single chip.
The gates of the FETs in memory cells “a”, “b” and “c” are all connected to the same word line WL(n−1), the gates of the FETs in memory cells “d”, “e” and “f” are all connected to the same word line WL(n), and the gates of the FETs in memory cells “g”, “h” and “i” are all connected to the same word line WL(n+1). Thus, a voltage applied to a given word line (WL) can affect many memory cells—namely all the memory cells connected to that word line.
Similarly, the sources of the FETs in memory cells “a”, “d” and “g” are all connected to the same bit line BL(n−1), the sources of the FETs in memory cells “b”, “e” and “h” are all connected to the same bit line BL(n), and the sources of the FETs in memory cells “c”, “f” and “i” are all connected to the same bit line BL(n+1). Thus, a voltage applied to a given bit line (BL) can affect many memory cells—namely all the memory cells connected to that word line.
Generally, to perform a write operation on a given memory cell, the appropriate wordline and bitline are “activated”. For example, to write a logic one in memory cell “e”, a voltage of 2 volts may be placed on WL(n), and a voltage of 1.2 volts may be placed on BL(n).
DRAM Performance Issues
FIG. 1C illustrates, schematically, a DRAM cell, such as a single one of the DRAM cells described with respect to FIG. 1B, comprising a FET (M1), and a storage capacitor. One of the source/drain diffusions (typically the source) of M1 is connected to a bitline, the other of the diffusions is connected to the storage capacitor. The gate of M1 is connected to a wordline.
The storage capacitor has a capacitance “Cn”. The bitline is a long conductor to which many DRAM cells may be connected. The bitline exhibits a capacitance “Cb1”.
A transfer ratio “T” may be defined, for charging the capacitor, as follows:T=Cn/(Cb1+Cn)
Generally, the idea is that when M1 is switched on, the bitline voltage (Vdd) can be “transferred” to the capacitor—to charge or discharge the capacitor. Generally, the two (binary) logic states for a DRAM are charged and not charged.
If the bitline capacitance Cb1 were very small, such as zero, the transfer ratio T would be one, since Cn/(Cb1+Cn) would be Cn/(0+Cn) which would be Cn/Cn=1.
If the bitline capacitance is large, the transfer ratio would be small. For example, if Cb1 were˜10 times Cn, then the transfer ratio would be Cn/((˜10*Cn)+Cn)=Cn/(˜11*Cn)˜=10%.
Historically, Cb1 is much larger than Cn, so the transfer ratio is typically very small.
For high performance DRAM (including eDRAM), it is known to use short bitlines, thereby decreasing the bitline capacitance Cb1 and improving the transfer ratio. However, by using many short bitlines instead of fewer longer bitlines, density (the number of devices which can be implemented in a given area) suffers.
Increasing the capacitance Cn of the storage capacitor is another way of improving transfer ratio, but this has its limitations too.
On the other hand, a smaller Cn can enable faster write of Vdd. This is due to the inherent “RC” time constant which is involved when charging a capacitor. Generally, the time required to charge a capacitor is related to the product of resistance “R” (which is desirably kept very low) times the capacitance “C”. Thus, the lower the capacitance,
A line coming down from the middle of M1 represents the “body” potential for the FET. This is what can be considered to be the “starting” voltage at the channel, which will work either “with” or “against” a voltage applied to the gate of the FET. Usually the body is grounded (zero volts). In some applications, a non-zero voltage may be applied to the body. Generally, with a body voltage of zero, the DRAM cell may have high performance, but may be leakier (less ability to retain the charge on the storage capacitor). On the other hand, the body voltage may be set to increase retention of charge on the storage capacitor, but generally only at the expense of reduced performance.
These (transfer ratio, performance, retention) are some of the issued related to DRAM and, as can be seen, there are numerous tradeoffs involved.
There are many applications for DRAM, with different requirements. It is not simply a matter of one DRAM being “better” than the other. Since there are always tradeoffs involved (such as performance versus retention), some applications can benefit from DRAM having higher performance with lower retention, and other applications can benefit from DRAM having higher retention with lower performance.
For example, there are different “levels” of cache memory (or simply “cache”). Cache memory is generally a temporary memory inserted between (for example) a very fast microprocessor with very little storage capability, and a mass storage device such as a hard disk which has very large storage capability but is very slow. In order to move data between these two entities (microprocessor and hard disk), cache memory can be inserted to temporarily store the data while, for example, the hard drive has time to write the data being sent to it by the microprocessor, freeing up the microprocessor for subsequent tasks. Generally, for example, some cache may be incorporated into the microprocessor, some may be external to the microprocessor, some cache may be on the motherboard, a hard disk may have its own cache associated therewith (clearly, external to the microprocessor), etc. And, data may pass through many levels of cache.
Physical Structure of DRAM cells
Generally, the DRAM cells discussed herein comprise a capacitor formed in a deep trench (DT) in a substrate, and an “access transistor” formed on the surface of the substrate adjacent and atop the capacitor. The capacitor (“DT capacitor”) generally comprises a first conductive region called the “buried plate” (or “counterelectrode”) which is a heavily doped region of the substrate surrounding the trench, a thin layer of insulating material such as oxide lining the trench, and a second conductive entity such as a heavily doped polycrystalline plug (or “node”) disposed within the trench. The transistor may comprise a FET having its drain (D) terminal connected to (or an extension of) the second electrode of the capacitor.
Regarding forming the buried plate of the DT capacitor, various techniques are known. For example, when forming a buried plate in a silicon trench, a layer of arsenic doped silicate glass (“ASG”) is disposed over a lower portion of the side walls of the trench using a Low Pressure Chemical Vapor Deposition (LPCVD) technique. The arsenic doped glass layer, when annealed, results in the diffusion of the arsenic into the silicon trench. In order to avoid increasing parasitic leakage currents along side walls of the trench, diffusion of the arsenic may be restricted to the lower portion of the trench, thereby avoiding diffusion of arsenic into the whole of the side walls of the silicon trench. It is therefore known to deposit an undoped glass layer over the trench using any suitable technique such as Chemical Vapor Deposition (CVD) technique. The undoped glass layer completely covers the side walls and the arsenic doped silicate glass layer in order to prevent arsenic escaping into the trench and causing an electrical connection which could short-circuit subsequently deposited electrodes. Separate stand-alone pieces of semiconductor processing equipment, sometimes known as tools or chambers, are used to deposit layers using the above-mentioned LPCVD and CVD techniques, respectively. See U.S. Pat. No. 6,316,310 (Siemens; 2001), incorporated by reference herein. Other techniques for forming a buried plate may include ion implantation, plasma doping, gas phase doping, solid phase doping, liquid phase doping.
FIG. 2 illustrates a DRAM cell 200 of the prior art, generally comprising an access transistor and an associated cell capacitor. Also shown is a wordline (WL), or “pass gate”, passing over the DT capacitor. The DRAM cell is generally formed, as follows.
Beginning with a semiconductor substrate 202, a deep trench (DT) 210 is formed, extending into the substrate 202, from a top (as viewed) surface thereof. The substrate 202 may comprise a SOI substrate having a layer 204 of silicon (SOI) on top of an insulating layer 206 which is atop an underlying silicon substrate 208. The insulating layer 206 typically comprises buried oxide (BOX). The deep trench (DT) 210 is for forming the cell capacitor (or “DT capacitor”), as follows. The trench 210 may have a width of about 50 nm to 200 nm and a depth of 1000 nm to 10000 nm, by way of example.
The cell capacitor generally comprises a first conductor called the “buried plate” which is a heavily doped region 212 of the substrate surrounding the trench 210, a thin layer 214 of insulating material lining the trench 210, and a second conductor 216 such as a heavily doped polycrystalline plug (or “node”, “DT poly”) disposed within the trench 210. A cell transistor (“access transistor”) 220 may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second conductor (node) of the capacitor, as follows.
The FET 220 comprises two spaced-apart diffusions, 222 and 224, within the surface of the substrate 202—one of which will serve as the “source” and the other of which will serve as the “drain” (D) of the transistor 220. The space between the two diffusion areas is called the “channel” (and is approximately where the legend “SOI” appears). A thin dielectric layer 226 is disposed on the substrate above the channel, and a “gate” structure (G) 228 is disposed over the dielectric layer 226, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) The gate 228 may be a portion of an elongate wordline, referred to (for this memory cell) as the “active wordline” (Active WL).
Generally, a plurality of DRAM/eDRAM memory cells in a given row of a memory array may utilize a given wordline as the gates for their access transistors. And the source diffusions of the DRAM/eDRAM memory cells in a given column of a memory array may utilize a given bitline as the sources (S) for their access transistors.
In modern CMOS technology, shallow trench isolation (STI) is commonly used to isolate one (or more) transistors from other transistors, for both logic and memory. As shown in FIG. 2, a shallow trench 232 may be formed, surrounding the access transistor 220 (only one side of the transistor is shown). Note that the trench 232 extends over the DT (node) poly 216, a top portion of which is adjacent the drain (D) of the transistor 220. Therefore, the trench 232 is less deep (thinner) over the DT poly 216 and immediately adjacent the drain (D) of the transistor 220, and may be deeper (thicker) further from the drain (D) of the transistor 220 (and, as shown, over top portion of the DT poly 216 which is distal from (not immediately adjacent to) the drain (D) of the transistor 220.
The STI trench 232 may be filled with an insulating material, such as oxide (STI oxide) 234. Because of the thin/thick trench geometry which has been described, the STI oxide will exhibit a thin portion 234a where it is proximal (adjacent to) the drain (D) of the transistor 220, and a thicker portion where it is distal from (not immediately adjacent to) the drain (D) of the transistor 220.
As mentioned above, a plurality of memory cells may be associated with a given word line (WL). Furthermore, the wordline may form the gates of the access transistors of those memory cells. In this example, the transistor 220 of the memory cell 200 is associated with the “active” wordline, which forms its gate (G). Another wordline, for another plurality of memory cells is shown, and is labeled “Pass WL” 240. And, as can be seen, the Pass WL 240 passes over the STI 234, above the node poly 216.
U.S. Pat. No. 4,688,063 (IBM, 1987), incorporated by reference herein, discloses dynamic ram cell with MOS trench capacitor in CMOS. This patent relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
US Patent Publication 20050280063 (IBM, 2005) discloses microelectronic element having trench capacitors with different capacitance values. A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface. As noted therein:                The present invention relates to microelectronic devices and processing, and more particularly to a microelectronic element and method for forming trench capacitors having different capacitance values on the same microelectronic element.        As the speed and circuit density of integrated circuits (“ICs” or “chips”) is increased from one generation to the next, a greater need exists for capacitive elements that are located close to logic circuits of a chip, or as parts of internal power supply circuits, for example. Thus, capacitive elements must often be provided on the same integrated circuit as such logic circuits and power supply circuits. Trench capacitors are used for storing data bits in some types of dynamic random access memories (DRAMs) and embedded DRAM (eDRAM) macros of chips that contain other functional elements such as processors. In such chips, the use of trench capacitors is favored for other purposes, e.g., to support logic circuits, and as parts of internal power supply circuits, because such other purpose trench capacitors can be formed at the same time as the trench capacitors of the DRAM or eDRAM. When a fairly large amount of capacitance is needed on a chip for such other purpose, a large number of trench capacitors are usually wired together, all having first plates held at a fixed potential such as ground and second plates wired together on which the potential is allowed to vary during operation or remains at a constant potential during operation. In such circumstances, significant usable area of an integrated circuit is occupied by an array of trench capacitors that are wired together of such purpose. Accordingly, the size of such array of trench capacitors is desirably made small, in order not to take up too much of the area of the integrated circuit.        One way of decreasing the size of such capacitor arrays is to enlarge the lateral, i.e. horizontal, dimensions of individual trench capacitors of the array, such as described in U.S. Pat. No. 6,566,191. For example, if the lateral dimension of the trench capacitor of a DRAM array is 90 nm in one lateral direction, the lateral dimension of a trench capacitor used for the different purpose, e.g., to support logic circuits, could be 135 nm, for example. However, the etching of trenches to different lateral dimensions is difficult. Reactive ion etching (RIE) of a hard mask layer and RIE of the underlying semiconductor substrate are difficult to adequately control when trenches having such different dimensions. In particular, the silicon profile control is difficult to maintain during an etching process for simultaneously etching trenches having two different lateral dimensions.        It would be desirable to provide a process of forming trench capacitors in which the lateral dimensions of the trench capacitors are substantially the same, such that the foregoing difficulties in etching are avoided.        